docs: rebuild system report and test workflow

fpga/run-linter.py

@@ -68,6 +68,13 @@ def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str], Set[str]]:
                 if not vlog.is_file():
                     print("Source file", vlog, "does not exist")
                     continue
+                # An expanded XCI may add DCP/VHDL/netlist artifacts to the
+                # project. They are not Verilog lint inputs; use the Verilog
+                # stub and regular RTL sources only.
+                if vlog.suffix.lower() not in (".v", ".sv", ".vh", ".svh", ".h"):
+                    continue
+                if vlog.name.lower().endswith(("_sim_netlist.v", "_sim_netlist.sv")):
+                    continue
                 vlog_target = target / vlog.relative_to(repo_root)
                 vlog_target.parent.mkdir(exist_ok=True, parents=True)
                 # shutil.copy(vlog, vlog_target)
@@ -234,7 +241,7 @@ def run_linter(prjdir: Path, topname: str, headerlist: Set[str], srclist: Set[st
     incargs = [ '-I' + i for i in inclist]
     args += incargs
     args += sorted(headerlist)
-    args += srclist
+    args += sorted(srclist)
 
     if os.name == "nt":
         response_args = [str(arg).replace("\\", "/") for arg in args[1:]]