docs: rebuild system report and test workflow

doc/reports/system/figures/verification_flow.dot

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+digraph G {
+  graph [rankdir=LR, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.55,
+         fontname="Noto Sans CJK SC"];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=9.5,
+        color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  rtl [label="RTL 静态检查\nVerilator lint"];
+  unit [label="模块级仿真\n协议、边界、反压"];
+  soc [label="SoC 仿真\nCPU + AXI + 加速器"];
+  impl [label="布局布线\n时序 / DRC / CDC / 资源"];
+  board [label="板级回归\n正确性 + 实测耗时"];
+  evidence [label="版本化证据\n日志 / rpt / bit / 指标文件", fillcolor="#D9EAF7"];
+
+  rtl -> unit -> soc -> impl -> board;
+  rtl -> evidence [style=dashed];
+  unit -> evidence [style=dashed];
+  soc -> evidence [style=dashed];
+  impl -> evidence [style=dashed];
+  board -> evidence [style=dashed];
+}