docs: rebuild system report and test workflow

doc/reports/system/figures/matmul_pipeline.dot

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+digraph G {
+  graph [rankdir=TB, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.38,
+         fontname="Noto Sans CJK SC"];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10,
+        color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  cfg [label="CPU 一次配置\n基址 / 组数 / stride", fillcolor="#EAF2F8"];
+  read [label="DMA 读取 128 B\nA、B → 空闲 Bank", fillcolor="#E8F3E8"];
+  calc [label="4 路 32x32 LUT 乘法\n每拍形成一个输出元素的 4 项乘积", fillcolor="#FFF1D6"];
+  write [label="DMA 写回 192 B\nC → ExtRAM", fillcolor="#E8F3E8"];
+  crc [label="硬件流水 CRC32\n不写回时仍可判定整批结果", fillcolor="#F8E6EA"];
+  next [label="Bank 翻转 / group+1", shape=diamond, fillcolor="#F2F2F2"];
+  done [label="done + dma_cycles", fillcolor="#D9EAF7"];
+
+  { rank=same; read; calc; write; }
+  cfg -> read;
+  read -> calc -> write;
+  write -> crc -> next;
+  next -> read [label="未完成", constraint=false];
+  next -> done [label="全部完成"];
+}