docs: rebuild system report and test workflow

doc/reports/system/figures/clock_cdc.dot

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+digraph G {
+  graph [rankdir=TB, bgcolor="transparent", pad=0.15, nodesep=0.30, ranksep=0.42,
+         fontname="Noto Sans CJK SC"];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10,
+        color="#44546A", fillcolor="#F7F8FA", margin="0.13,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  osc [label="50 MHz 外部时钟"];
+  pll [label="PLL\nlocked", fillcolor="#D9EAF7"];
+  cpu [label="cpu_clk 33.333 MHz\nCPU + AXI CPU 侧", fillcolor="#EAF2F8"];
+  sys [label="sys_clk 50 MHz\nCrossbar / DMA / FFT / matmul", fillcolor="#E8F3E8"];
+  mlk [label="mlkem_clk 76.923 MHz\nML-KEM 计算域", fillcolor="#F8E6EA"];
+  cdc_cpu [label="CPU↔SYS AXI CDC\n异步握手 / FIFO", shape=box, fillcolor="#FFF1D6"];
+  cdc_mlk [label="SYS↔ML-KEM CDC\n命令 / 数据 / 状态同步", shape=box, fillcolor="#FFF1D6"];
+  rst [label="各域复位同步器\n异步置位、同步释放", fillcolor="#F2F2F2"];
+
+  { rank=same; osc; pll; }
+  { rank=same; cpu; cdc_cpu; sys; }
+  { rank=same; cdc_mlk; mlk; }
+  osc -> pll;
+  pll -> cpu;
+  pll -> sys;
+  pll -> mlk;
+  cpu -> cdc_cpu -> sys [dir=both];
+  sys -> cdc_mlk -> mlk [dir=both];
+  pll -> rst [label="locked"];
+  rst -> cpu [style=dashed, label="resetn", constraint=false];
+  rst -> sys [style=dashed, label="resetn", constraint=false];
+  rst -> mlk [style=dashed, label="resetn", constraint=false];
+}

doc/reports/system/figures/matmul_pipeline.dot

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+digraph G {
+  graph [rankdir=TB, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.38,
+         fontname="Noto Sans CJK SC"];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10,
+        color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  cfg [label="CPU 一次配置\n基址 / 组数 / stride", fillcolor="#EAF2F8"];
+  read [label="DMA 读取 128 B\nA、B → 空闲 Bank", fillcolor="#E8F3E8"];
+  calc [label="4 路 32x32 LUT 乘法\n每拍形成一个输出元素的 4 项乘积", fillcolor="#FFF1D6"];
+  write [label="DMA 写回 192 B\nC → ExtRAM", fillcolor="#E8F3E8"];
+  crc [label="硬件流水 CRC32\n不写回时仍可判定整批结果", fillcolor="#F8E6EA"];
+  next [label="Bank 翻转 / group+1", shape=diamond, fillcolor="#F2F2F2"];
+  done [label="done + dma_cycles", fillcolor="#D9EAF7"];
+
+  { rank=same; read; calc; write; }
+  cfg -> read;
+  read -> calc -> write;
+  write -> crc -> next;
+  next -> read [label="未完成", constraint=false];
+  next -> done [label="全部完成"];
+}

doc/reports/system/figures/system_boundary.dot

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+digraph G {
+  graph [rankdir=LR, bgcolor="transparent", pad=0.15, nodesep=0.35, ranksep=0.65,
+         fontname="Noto Sans CJK SC", fontsize=10];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=10,
+        color="#44546A", fillcolor="#F5F7FA", margin="0.13,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  cpu [label="LoongArch32r CPU\n软件调度 / 校验", fillcolor="#EAF2F8"];
+  xbar [label="AXI Crossbar\n双主设备 / 统一编址", fillcolor="#D9EAF7"];
+  mem [label="BaseRAM / ExtRAM", fillcolor="#F2F2F2"];
+  periph [label="UART / DVI / confreg", fillcolor="#F2F2F2"];
+  dma [label="4 通道 DMA\nmem2mem / endpoint", fillcolor="#E8F3E8"];
+  seq [label="matmul 批处理序列器", fillcolor="#E8F3E8"];
+  matmul [label="4x4 矩阵乘法\n双 Bank + CRC", fillcolor="#FFF1D6"];
+  fft [label="1024 点 FFT\n5 个 Radix-2² SDF 单元", fillcolor="#FFF1D6"];
+  mlkem [label="ML-KEM-512/768/1024\nKeyGen / Encaps / Decaps", fillcolor="#F8E6EA"];
+
+  cpu -> xbar [label="AXI master 0"];
+  dma -> xbar [label="AXI master 1", dir=both];
+  xbar -> mem [dir=both];
+  xbar -> periph [dir=both];
+  xbar -> dma [label="配置"];
+  xbar -> matmul [label="Slave 7", dir=both];
+  xbar -> fft [label="Slave 6 / 高地址", dir=both];
+  xbar -> mlkem [label="Slave 6 / 低地址", dir=both];
+  seq -> dma [label="描述符"];
+  seq -> matmul [label="start / done"];
+  dma -> matmul [label="本地 endpoint", dir=both, color="#2F6B3C", penwidth=1.4];
+}

doc/reports/system/figures/verification_flow.dot

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+digraph G {
+  graph [rankdir=LR, bgcolor="transparent", pad=0.15, nodesep=0.28, ranksep=0.55,
+         fontname="Noto Sans CJK SC"];
+  node [shape=box, style="rounded,filled", fontname="Noto Sans CJK SC", fontsize=9.5,
+        color="#44546A", fillcolor="#F7F8FA", margin="0.12,0.08"];
+  edge [fontname="Noto Sans CJK SC", fontsize=9, color="#596777", arrowsize=0.7];
+
+  rtl [label="RTL 静态检查\nVerilator lint"];
+  unit [label="模块级仿真\n协议、边界、反压"];
+  soc [label="SoC 仿真\nCPU + AXI + 加速器"];
+  impl [label="布局布线\n时序 / DRC / CDC / 资源"];
+  board [label="板级回归\n正确性 + 实测耗时"];
+  evidence [label="版本化证据\n日志 / rpt / bit / 指标文件", fillcolor="#D9EAF7"];
+
+  rtl -> unit -> soc -> impl -> board;
+  rtl -> evidence [style=dashed];
+  unit -> evidence [style=dashed];
+  soc -> evidence [style=dashed];
+  impl -> evidence [style=dashed];
+  board -> evidence [style=dashed];
+}