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mlkem test diagnostics and allocator updates

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This commit is contained in:
FallenSigh
2026-07-08 02:35:56 +08:00
parent 65607badd2
commit 0c85a20b4e
40 changed files with 37168 additions and 2093 deletions
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638
rtl/soc_top.v
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@@ -83,6 +83,8 @@ wire cpu_clk;
wire cpu_resetn;
wire sys_clk;
wire sys_resetn;
wire mlkem_clk;
wire mlkem_resetn;
wire pll_locked;
generate if(SIMULATION) begin: sim_clk
@@ -91,25 +93,32 @@ generate if(SIMULATION) begin: sim_clk
initial begin
clk_sim = 1'b0;
end
always #15 clk_sim = ~clk_sim;
assign cpu_clk = clk_sim;
assign sys_clk = clk;
rst_sync u_rst_sys(
.clk(sys_clk),
.rst_n_in(~reset),
.rst_n_out(sys_resetn)
);
always #15 clk_sim = ~clk_sim;
assign cpu_clk = clk_sim;
assign sys_clk = clk;
assign mlkem_clk = sys_clk;
rst_sync u_rst_sys(
.clk(sys_clk),
.rst_n_in(~reset),
.rst_n_out(sys_resetn)
);
rst_sync u_rst_cpu(
.clk(cpu_clk),
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
end
else begin: pll_clk
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
rst_sync u_rst_mlkem(
.clk(mlkem_clk),
.rst_n_in(sys_resetn),
.rst_n_out(mlkem_resetn)
);
end
else begin: pll_clk
clk_pll u_clk_pll(
.cpu_clk (cpu_clk),
.sys_clk (sys_clk),
.mlkem_clk (mlkem_clk),
.resetn (~reset),
.locked (pll_locked),
.clk_in1 (clk)
@@ -124,6 +133,11 @@ else begin: pll_clk
.rst_n_in(sys_resetn),
.rst_n_out(cpu_resetn)
);
rst_sync u_rst_mlkem(
.clk(mlkem_clk),
.rst_n_in(sys_resetn),
.rst_n_out(mlkem_resetn)
);
end
endgenerate
@@ -393,15 +407,15 @@ wire dma_s_wlast ;
wire dma_s_wvalid ;
wire dma_s_wready ;
wire [4 :0] dma_s_bid ;
wire [1 :0] dma_s_bresp ;
wire dma_s_bvalid ;
wire dma_s_bready ;
wire dma_finish ;
wire cdma_dma_finish;
wire cdma_matmul_seq_irq;
assign dma_finish = cdma_dma_finish | cdma_matmul_seq_irq;
// reserved
wire [1 :0] dma_s_bresp ;
wire dma_s_bvalid ;
wire dma_s_bready ;
wire dma_finish ;
wire cdma_dma_finish;
wire cdma_matmul_seq_irq;
assign dma_finish = cdma_dma_finish | cdma_matmul_seq_irq;
// reserved
wire [4 :0] axiOut_1_arid ;
wire [31:0] axiOut_1_araddr ;
wire [7 :0] axiOut_1_arlen ;
@@ -565,7 +579,7 @@ wire [4 :0] fft_bid ;
wire [1 :0] fft_bresp ;
wire fft_bvalid ;
wire fft_bready ;
wire fft_finish;
wire fft_finish;
//slave 7
wire [4 :0] axiOut_7_arid ;
@@ -606,24 +620,24 @@ wire axiOut_7_bvalid ;
wire axiOut_7_bready ;
wire confreg_int;
wire matmul_intr;
wire matmul_ep_wr_valid;
wire [3:0] matmul_ep_wr_id;
wire [3:0] matmul_ep_wr_bank;
wire [7:0] matmul_ep_wr_word_addr;
wire [31:0] matmul_ep_wr_data;
wire matmul_ep_wr_ready;
wire matmul_ep_rd_valid;
wire [3:0] matmul_ep_rd_id;
wire [3:0] matmul_ep_rd_bank;
wire [7:0] matmul_ep_rd_word_addr;
wire [31:0] matmul_ep_rd_data;
wire matmul_ep_rd_ready;
wire matmul_direct_start_valid;
wire matmul_direct_start_bank;
wire matmul_direct_done_clear;
wire matmul_direct_crc_clear;
wire matmul_direct_done;
wire matmul_intr;
wire matmul_ep_wr_valid;
wire [3:0] matmul_ep_wr_id;
wire [3:0] matmul_ep_wr_bank;
wire [7:0] matmul_ep_wr_word_addr;
wire [31:0] matmul_ep_wr_data;
wire matmul_ep_wr_ready;
wire matmul_ep_rd_valid;
wire [3:0] matmul_ep_rd_id;
wire [3:0] matmul_ep_rd_bank;
wire [7:0] matmul_ep_rd_word_addr;
wire [31:0] matmul_ep_rd_data;
wire matmul_ep_rd_ready;
wire matmul_direct_start_valid;
wire matmul_direct_start_bank;
wire matmul_direct_done_clear;
wire matmul_direct_crc_clear;
wire matmul_direct_done;
wire mlkem_intr;
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
@@ -1446,12 +1460,14 @@ axi_dvi u_axi_dvi (
);
// slave 6 - shared FFT / ML-KEM accelerator window (0x1f400000, virtual 0xbf400000)
// ML-KEM: 0x0000..0x0114
// FFT: 0x1000/0x2000/0x3000/0x4000/0xf000
// PRNG: 0xd000..0xd010
// ML-KEM: 0x0000..0x3fff
// FFT: 0x8000..0xcfff
fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
.clk (sys_clk),
.resetn (sys_resetn),
.mlkem_clk (mlkem_clk),
.mlkem_resetn (mlkem_resetn),
.s_axi_awid (fft_awid ),
.s_axi_awaddr (fft_awaddr ),
@@ -1491,12 +1507,12 @@ fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
.s_axi_rdata (fft_rdata ),
.s_axi_rresp (fft_rresp ),
.s_axi_rlast (fft_rlast ),
.s_axi_rvalid (fft_rvalid),
.s_axi_rready (fft_rready),
.fft_finish (fft_finish),
.mlkem_intr (mlkem_intr)
);
.s_axi_rvalid (fft_rvalid),
.s_axi_rready (fft_rready),
.fft_finish (fft_finish),
.mlkem_intr (mlkem_intr)
);
//slave 7 - matmul accelerator
matmul_axi_slave u_matmul_axi_slave (
@@ -1537,35 +1553,35 @@ matmul_axi_slave u_matmul_axi_slave (
.s_axi_arvalid (axiOut_7_arvalid),
.s_axi_arready (axiOut_7_arready),
.s_axi_rid (axiOut_7_rid ),
.s_axi_rdata (axiOut_7_rdata ),
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr(matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr(matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.mat_start_valid(matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.intr (matmul_intr)
);
.s_axi_rid (axiOut_7_rid ),
.s_axi_rdata (axiOut_7_rdata ),
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr(matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr(matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.mat_start_valid(matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.intr (matmul_intr)
);
wire [31:0] cdma_s_awaddr;
wire [2:0] cdma_s_awprot;
@@ -1583,121 +1599,121 @@ wire [2:0] cdma_s_arprot;
wire cdma_s_arvalid;
wire cdma_s_arready;
wire [31:0] cdma_s_rdata;
wire [1:0] cdma_s_rresp;
wire cdma_s_rvalid;
wire cdma_s_rready;
wire [31:0] cdma_mux_awaddr;
wire cdma_mux_awvalid;
wire cdma_mux_awready;
wire [31:0] cdma_mux_wdata;
wire [3:0] cdma_mux_wstrb;
wire cdma_mux_wvalid;
wire cdma_mux_wready;
wire [1:0] cdma_mux_bresp;
wire cdma_mux_bvalid;
wire cdma_mux_bready;
wire [31:0] cdma_mux_araddr;
wire cdma_mux_arvalid;
wire cdma_mux_arready;
wire [31:0] cdma_mux_rdata;
wire [1:0] cdma_mux_rresp;
wire cdma_mux_rvalid;
wire cdma_mux_rready;
wire [31:0] cdma_bridge_awaddr;
wire cdma_bridge_awvalid;
wire cdma_bridge_awready;
wire [31:0] cdma_bridge_wdata;
wire [3:0] cdma_bridge_wstrb;
wire cdma_bridge_wvalid;
wire cdma_bridge_wready;
wire [1:0] cdma_bridge_bresp;
wire cdma_bridge_bvalid;
wire cdma_bridge_bready;
wire [31:0] cdma_bridge_araddr;
wire cdma_bridge_arvalid;
wire cdma_bridge_arready;
wire [31:0] cdma_bridge_rdata;
wire [1:0] cdma_bridge_rresp;
wire cdma_bridge_rvalid;
wire cdma_bridge_rready;
wire bridge_cdma_rd_req_valid;
wire bridge_cdma_rd_req_ready;
wire [31:0] bridge_cdma_rd_req_src;
wire [31:0] bridge_cdma_rd_req_bytes;
wire [3:0] bridge_cdma_rd_req_ep_id;
wire [3:0] bridge_cdma_rd_req_ep_bank;
wire [7:0] bridge_cdma_rd_req_ep_word_off;
wire bridge_cdma_rd_req_done;
wire bridge_cdma_wr_req_valid;
wire bridge_cdma_wr_req_ready;
wire [31:0] bridge_cdma_wr_req_dst;
wire [31:0] bridge_cdma_wr_req_bytes;
wire [3:0] bridge_cdma_wr_req_ep_id;
wire [3:0] bridge_cdma_wr_req_ep_bank;
wire [7:0] bridge_cdma_wr_req_ep_word_off;
wire bridge_cdma_wr_req_done;
wire cdma_axil_wr_bridge = (cdma_s_awaddr[11:8] == 4'h2);
wire cdma_axil_rd_bridge = (cdma_s_araddr[11:8] == 4'h2);
reg cdma_axil_wr_active;
reg cdma_axil_wr_bridge_hold;
reg cdma_axil_b_bridge;
reg cdma_axil_r_bridge;
wire cdma_axil_wr_sel = cdma_axil_wr_active ? cdma_axil_wr_bridge_hold : cdma_axil_wr_bridge;
assign cdma_mux_awaddr = cdma_s_awaddr;
assign cdma_mux_awvalid = cdma_s_awvalid && !cdma_axil_wr_sel;
assign cdma_mux_wdata = cdma_s_wdata;
assign cdma_mux_wstrb = cdma_s_wstrb;
assign cdma_mux_wvalid = cdma_s_wvalid && !cdma_axil_wr_sel;
assign cdma_mux_bready = cdma_s_bready && !cdma_axil_b_bridge;
assign cdma_mux_araddr = cdma_s_araddr;
assign cdma_mux_arvalid = cdma_s_arvalid && !cdma_axil_rd_bridge;
assign cdma_mux_rready = cdma_s_rready && !cdma_axil_r_bridge;
assign cdma_bridge_awaddr = cdma_s_awaddr;
assign cdma_bridge_awvalid = cdma_s_awvalid && cdma_axil_wr_sel;
assign cdma_bridge_wdata = cdma_s_wdata;
assign cdma_bridge_wstrb = cdma_s_wstrb;
assign cdma_bridge_wvalid = cdma_s_wvalid && cdma_axil_wr_sel;
assign cdma_bridge_bready = cdma_s_bready && cdma_axil_b_bridge;
assign cdma_bridge_araddr = cdma_s_araddr;
assign cdma_bridge_arvalid = cdma_s_arvalid && cdma_axil_rd_bridge;
assign cdma_bridge_rready = cdma_s_rready && cdma_axil_r_bridge;
assign cdma_s_awready = cdma_axil_wr_sel ? cdma_bridge_awready : cdma_mux_awready;
assign cdma_s_wready = cdma_axil_wr_sel ? cdma_bridge_wready : cdma_mux_wready;
assign cdma_s_bresp = cdma_axil_b_bridge ? cdma_bridge_bresp : cdma_mux_bresp;
assign cdma_s_bvalid = cdma_axil_b_bridge ? cdma_bridge_bvalid : cdma_mux_bvalid;
assign cdma_s_arready = cdma_axil_rd_bridge ? cdma_bridge_arready : cdma_mux_arready;
assign cdma_s_rdata = cdma_axil_r_bridge ? cdma_bridge_rdata : cdma_mux_rdata;
assign cdma_s_rresp = cdma_axil_r_bridge ? cdma_bridge_rresp : cdma_mux_rresp;
assign cdma_s_rvalid = cdma_axil_r_bridge ? cdma_bridge_rvalid : cdma_mux_rvalid;
always @(posedge sys_clk) begin
if (!sys_resetn) begin
cdma_axil_wr_active <= 1'b0;
cdma_axil_wr_bridge_hold <= 1'b0;
cdma_axil_b_bridge <= 1'b0;
cdma_axil_r_bridge <= 1'b0;
end else begin
if (cdma_s_awvalid && !cdma_axil_wr_active) begin
cdma_axil_wr_active <= 1'b1;
cdma_axil_wr_bridge_hold <= cdma_axil_wr_bridge;
end
if (cdma_s_awvalid && cdma_s_awready && cdma_s_wvalid && cdma_s_wready) begin
cdma_axil_b_bridge <= cdma_axil_wr_sel;
cdma_axil_wr_active <= 1'b0;
end
if (cdma_s_arvalid && cdma_s_arready)
cdma_axil_r_bridge <= cdma_axil_rd_bridge;
end
end
axi_axil_adapter #(
wire [1:0] cdma_s_rresp;
wire cdma_s_rvalid;
wire cdma_s_rready;
wire [31:0] cdma_mux_awaddr;
wire cdma_mux_awvalid;
wire cdma_mux_awready;
wire [31:0] cdma_mux_wdata;
wire [3:0] cdma_mux_wstrb;
wire cdma_mux_wvalid;
wire cdma_mux_wready;
wire [1:0] cdma_mux_bresp;
wire cdma_mux_bvalid;
wire cdma_mux_bready;
wire [31:0] cdma_mux_araddr;
wire cdma_mux_arvalid;
wire cdma_mux_arready;
wire [31:0] cdma_mux_rdata;
wire [1:0] cdma_mux_rresp;
wire cdma_mux_rvalid;
wire cdma_mux_rready;
wire [31:0] cdma_bridge_awaddr;
wire cdma_bridge_awvalid;
wire cdma_bridge_awready;
wire [31:0] cdma_bridge_wdata;
wire [3:0] cdma_bridge_wstrb;
wire cdma_bridge_wvalid;
wire cdma_bridge_wready;
wire [1:0] cdma_bridge_bresp;
wire cdma_bridge_bvalid;
wire cdma_bridge_bready;
wire [31:0] cdma_bridge_araddr;
wire cdma_bridge_arvalid;
wire cdma_bridge_arready;
wire [31:0] cdma_bridge_rdata;
wire [1:0] cdma_bridge_rresp;
wire cdma_bridge_rvalid;
wire cdma_bridge_rready;
wire bridge_cdma_rd_req_valid;
wire bridge_cdma_rd_req_ready;
wire [31:0] bridge_cdma_rd_req_src;
wire [31:0] bridge_cdma_rd_req_bytes;
wire [3:0] bridge_cdma_rd_req_ep_id;
wire [3:0] bridge_cdma_rd_req_ep_bank;
wire [7:0] bridge_cdma_rd_req_ep_word_off;
wire bridge_cdma_rd_req_done;
wire bridge_cdma_wr_req_valid;
wire bridge_cdma_wr_req_ready;
wire [31:0] bridge_cdma_wr_req_dst;
wire [31:0] bridge_cdma_wr_req_bytes;
wire [3:0] bridge_cdma_wr_req_ep_id;
wire [3:0] bridge_cdma_wr_req_ep_bank;
wire [7:0] bridge_cdma_wr_req_ep_word_off;
wire bridge_cdma_wr_req_done;
wire cdma_axil_wr_bridge = (cdma_s_awaddr[11:8] == 4'h2);
wire cdma_axil_rd_bridge = (cdma_s_araddr[11:8] == 4'h2);
reg cdma_axil_wr_active;
reg cdma_axil_wr_bridge_hold;
reg cdma_axil_b_bridge;
reg cdma_axil_r_bridge;
wire cdma_axil_wr_sel = cdma_axil_wr_active ? cdma_axil_wr_bridge_hold : cdma_axil_wr_bridge;
assign cdma_mux_awaddr = cdma_s_awaddr;
assign cdma_mux_awvalid = cdma_s_awvalid && !cdma_axil_wr_sel;
assign cdma_mux_wdata = cdma_s_wdata;
assign cdma_mux_wstrb = cdma_s_wstrb;
assign cdma_mux_wvalid = cdma_s_wvalid && !cdma_axil_wr_sel;
assign cdma_mux_bready = cdma_s_bready && !cdma_axil_b_bridge;
assign cdma_mux_araddr = cdma_s_araddr;
assign cdma_mux_arvalid = cdma_s_arvalid && !cdma_axil_rd_bridge;
assign cdma_mux_rready = cdma_s_rready && !cdma_axil_r_bridge;
assign cdma_bridge_awaddr = cdma_s_awaddr;
assign cdma_bridge_awvalid = cdma_s_awvalid && cdma_axil_wr_sel;
assign cdma_bridge_wdata = cdma_s_wdata;
assign cdma_bridge_wstrb = cdma_s_wstrb;
assign cdma_bridge_wvalid = cdma_s_wvalid && cdma_axil_wr_sel;
assign cdma_bridge_bready = cdma_s_bready && cdma_axil_b_bridge;
assign cdma_bridge_araddr = cdma_s_araddr;
assign cdma_bridge_arvalid = cdma_s_arvalid && cdma_axil_rd_bridge;
assign cdma_bridge_rready = cdma_s_rready && cdma_axil_r_bridge;
assign cdma_s_awready = cdma_axil_wr_sel ? cdma_bridge_awready : cdma_mux_awready;
assign cdma_s_wready = cdma_axil_wr_sel ? cdma_bridge_wready : cdma_mux_wready;
assign cdma_s_bresp = cdma_axil_b_bridge ? cdma_bridge_bresp : cdma_mux_bresp;
assign cdma_s_bvalid = cdma_axil_b_bridge ? cdma_bridge_bvalid : cdma_mux_bvalid;
assign cdma_s_arready = cdma_axil_rd_bridge ? cdma_bridge_arready : cdma_mux_arready;
assign cdma_s_rdata = cdma_axil_r_bridge ? cdma_bridge_rdata : cdma_mux_rdata;
assign cdma_s_rresp = cdma_axil_r_bridge ? cdma_bridge_rresp : cdma_mux_rresp;
assign cdma_s_rvalid = cdma_axil_r_bridge ? cdma_bridge_rvalid : cdma_mux_rvalid;
always @(posedge sys_clk) begin
if (!sys_resetn) begin
cdma_axil_wr_active <= 1'b0;
cdma_axil_wr_bridge_hold <= 1'b0;
cdma_axil_b_bridge <= 1'b0;
cdma_axil_r_bridge <= 1'b0;
end else begin
if (cdma_s_awvalid && !cdma_axil_wr_active) begin
cdma_axil_wr_active <= 1'b1;
cdma_axil_wr_bridge_hold <= cdma_axil_wr_bridge;
end
if (cdma_s_awvalid && cdma_s_awready && cdma_s_wvalid && cdma_s_wready) begin
cdma_axil_b_bridge <= cdma_axil_wr_sel;
cdma_axil_wr_active <= 1'b0;
end
if (cdma_s_arvalid && cdma_s_arready)
cdma_axil_r_bridge <= cdma_axil_rd_bridge;
end
end
axi_axil_adapter #(
.ADDR_WIDTH(32),
.AXI_DATA_WIDTH(32),
.AXI_ID_WIDTH(5),
@@ -1762,63 +1778,63 @@ u_axi_axil_adapter(
.m_axil_rdata(cdma_s_rdata),
.m_axil_rresp(cdma_s_rresp),
.m_axil_rvalid(cdma_s_rvalid),
.m_axil_rready(cdma_s_rready)
);
cdma_matmul_bridge #(
.ADDR_WIDTH (32),
.AXIL_ADDR_WIDTH (32),
.AXIL_DATA_WIDTH (32)
) u_cdma_matmul_bridge (
.clk (sys_clk),
.rst_n (sys_resetn),
.s_axil_awaddr (cdma_bridge_awaddr),
.s_axil_awvalid (cdma_bridge_awvalid),
.s_axil_awready (cdma_bridge_awready),
.s_axil_wdata (cdma_bridge_wdata),
.s_axil_wstrb (cdma_bridge_wstrb),
.s_axil_wvalid (cdma_bridge_wvalid),
.s_axil_wready (cdma_bridge_wready),
.s_axil_bresp (cdma_bridge_bresp),
.s_axil_bvalid (cdma_bridge_bvalid),
.s_axil_bready (cdma_bridge_bready),
.s_axil_araddr (cdma_bridge_araddr),
.s_axil_arvalid (cdma_bridge_arvalid),
.s_axil_arready (cdma_bridge_arready),
.s_axil_rdata (cdma_bridge_rdata),
.s_axil_rresp (cdma_bridge_rresp),
.s_axil_rvalid (cdma_bridge_rvalid),
.s_axil_rready (cdma_bridge_rready),
.cdma_rd_req_valid (bridge_cdma_rd_req_valid),
.cdma_rd_req_ready (bridge_cdma_rd_req_ready),
.cdma_rd_req_src (bridge_cdma_rd_req_src),
.cdma_rd_req_bytes (bridge_cdma_rd_req_bytes),
.cdma_rd_req_ep_id (bridge_cdma_rd_req_ep_id),
.cdma_rd_req_ep_bank (bridge_cdma_rd_req_ep_bank),
.cdma_rd_req_ep_word_off(bridge_cdma_rd_req_ep_word_off),
.cdma_rd_req_done (bridge_cdma_rd_req_done),
.cdma_wr_req_valid (bridge_cdma_wr_req_valid),
.cdma_wr_req_ready (bridge_cdma_wr_req_ready),
.cdma_wr_req_dst (bridge_cdma_wr_req_dst),
.cdma_wr_req_bytes (bridge_cdma_wr_req_bytes),
.cdma_wr_req_ep_id (bridge_cdma_wr_req_ep_id),
.cdma_wr_req_ep_bank (bridge_cdma_wr_req_ep_bank),
.cdma_wr_req_ep_word_off(bridge_cdma_wr_req_ep_word_off),
.cdma_wr_req_done (bridge_cdma_wr_req_done),
.mat_start_valid (matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.seq_done_irq (cdma_matmul_seq_irq)
);
// 8 通道 DMA
snix_axil_cdma_mux #(
.m_axil_rready(cdma_s_rready)
);
cdma_matmul_bridge #(
.ADDR_WIDTH (32),
.AXIL_ADDR_WIDTH (32),
.AXIL_DATA_WIDTH (32)
) u_cdma_matmul_bridge (
.clk (sys_clk),
.rst_n (sys_resetn),
.s_axil_awaddr (cdma_bridge_awaddr),
.s_axil_awvalid (cdma_bridge_awvalid),
.s_axil_awready (cdma_bridge_awready),
.s_axil_wdata (cdma_bridge_wdata),
.s_axil_wstrb (cdma_bridge_wstrb),
.s_axil_wvalid (cdma_bridge_wvalid),
.s_axil_wready (cdma_bridge_wready),
.s_axil_bresp (cdma_bridge_bresp),
.s_axil_bvalid (cdma_bridge_bvalid),
.s_axil_bready (cdma_bridge_bready),
.s_axil_araddr (cdma_bridge_araddr),
.s_axil_arvalid (cdma_bridge_arvalid),
.s_axil_arready (cdma_bridge_arready),
.s_axil_rdata (cdma_bridge_rdata),
.s_axil_rresp (cdma_bridge_rresp),
.s_axil_rvalid (cdma_bridge_rvalid),
.s_axil_rready (cdma_bridge_rready),
.cdma_rd_req_valid (bridge_cdma_rd_req_valid),
.cdma_rd_req_ready (bridge_cdma_rd_req_ready),
.cdma_rd_req_src (bridge_cdma_rd_req_src),
.cdma_rd_req_bytes (bridge_cdma_rd_req_bytes),
.cdma_rd_req_ep_id (bridge_cdma_rd_req_ep_id),
.cdma_rd_req_ep_bank (bridge_cdma_rd_req_ep_bank),
.cdma_rd_req_ep_word_off(bridge_cdma_rd_req_ep_word_off),
.cdma_rd_req_done (bridge_cdma_rd_req_done),
.cdma_wr_req_valid (bridge_cdma_wr_req_valid),
.cdma_wr_req_ready (bridge_cdma_wr_req_ready),
.cdma_wr_req_dst (bridge_cdma_wr_req_dst),
.cdma_wr_req_bytes (bridge_cdma_wr_req_bytes),
.cdma_wr_req_ep_id (bridge_cdma_wr_req_ep_id),
.cdma_wr_req_ep_bank (bridge_cdma_wr_req_ep_bank),
.cdma_wr_req_ep_word_off(bridge_cdma_wr_req_ep_word_off),
.cdma_wr_req_done (bridge_cdma_wr_req_done),
.mat_start_valid (matmul_direct_start_valid),
.mat_start_bank (matmul_direct_start_bank),
.mat_done_clear (matmul_direct_done_clear),
.mat_crc_clear (matmul_direct_crc_clear),
.mat_done (matmul_direct_done),
.seq_done_irq (cdma_matmul_seq_irq)
);
// 8 通道 DMA
snix_axil_cdma_mux #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32), // 适配你的 32-bit 总线
.AXIL_ADDR_WIDTH (32),
@@ -1832,23 +1848,23 @@ snix_axil_cdma_mux #(
.rst_n (sys_resetn), // 低电平复位
// AXI-Lite 从机接口 (接 CPU 发来的配置请求)
.s_axil_awaddr (cdma_mux_awaddr),
.s_axil_awvalid (cdma_mux_awvalid),
.s_axil_awready (cdma_mux_awready),
.s_axil_wdata (cdma_mux_wdata),
.s_axil_wstrb (cdma_mux_wstrb),
.s_axil_wvalid (cdma_mux_wvalid),
.s_axil_wready (cdma_mux_wready),
.s_axil_bresp (cdma_mux_bresp),
.s_axil_bvalid (cdma_mux_bvalid),
.s_axil_bready (cdma_mux_bready),
.s_axil_araddr (cdma_mux_araddr),
.s_axil_arvalid (cdma_mux_arvalid),
.s_axil_arready (cdma_mux_arready),
.s_axil_rdata (cdma_mux_rdata),
.s_axil_rresp (cdma_mux_rresp),
.s_axil_rvalid (cdma_mux_rvalid),
.s_axil_rready (cdma_mux_rready),
.s_axil_awaddr (cdma_mux_awaddr),
.s_axil_awvalid (cdma_mux_awvalid),
.s_axil_awready (cdma_mux_awready),
.s_axil_wdata (cdma_mux_wdata),
.s_axil_wstrb (cdma_mux_wstrb),
.s_axil_wvalid (cdma_mux_wvalid),
.s_axil_wready (cdma_mux_wready),
.s_axil_bresp (cdma_mux_bresp),
.s_axil_bvalid (cdma_mux_bvalid),
.s_axil_bready (cdma_mux_bready),
.s_axil_araddr (cdma_mux_araddr),
.s_axil_arvalid (cdma_mux_arvalid),
.s_axil_arready (cdma_mux_arready),
.s_axil_rdata (cdma_mux_rdata),
.s_axil_rresp (cdma_mux_rresp),
.s_axil_rvalid (cdma_mux_rvalid),
.s_axil_rready (cdma_mux_rready),
// AXI4 主机接口 (接 Crossbar 去搬运数据)
.mm2mm_awid (dma_m_awid),
@@ -1891,43 +1907,43 @@ snix_axil_cdma_mux #(
.mm2mm_rresp (dma_m_rresp),
.mm2mm_rlast (dma_m_rlast),
.mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
// 本地直连到 matmul，不经过 AXI crossbar
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr (matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr (matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.ext_rd_req_valid (bridge_cdma_rd_req_valid),
.ext_rd_req_ready (bridge_cdma_rd_req_ready),
.ext_rd_req_src (bridge_cdma_rd_req_src),
.ext_rd_req_bytes (bridge_cdma_rd_req_bytes),
.ext_rd_req_ep_id (bridge_cdma_rd_req_ep_id),
.ext_rd_req_ep_bank (bridge_cdma_rd_req_ep_bank),
.ext_rd_req_ep_word_off(bridge_cdma_rd_req_ep_word_off),
.ext_rd_req_done (bridge_cdma_rd_req_done),
.ext_wr_req_valid (bridge_cdma_wr_req_valid),
.ext_wr_req_ready (bridge_cdma_wr_req_ready),
.ext_wr_req_dst (bridge_cdma_wr_req_dst),
.ext_wr_req_bytes (bridge_cdma_wr_req_bytes),
.ext_wr_req_ep_id (bridge_cdma_wr_req_ep_id),
.ext_wr_req_ep_bank (bridge_cdma_wr_req_ep_bank),
.ext_wr_req_ep_word_off(bridge_cdma_wr_req_ep_word_off),
.ext_wr_req_done (bridge_cdma_wr_req_done),
// 全局中断输出
.dma_finish (cdma_dma_finish)
);
endmodule
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
// 本地直连到 matmul，不经过 AXI crossbar
.ep_wr_valid (matmul_ep_wr_valid),
.ep_wr_id (matmul_ep_wr_id),
.ep_wr_bank (matmul_ep_wr_bank),
.ep_wr_word_addr (matmul_ep_wr_word_addr),
.ep_wr_data (matmul_ep_wr_data),
.ep_wr_ready (matmul_ep_wr_ready),
.ep_rd_valid (matmul_ep_rd_valid),
.ep_rd_id (matmul_ep_rd_id),
.ep_rd_bank (matmul_ep_rd_bank),
.ep_rd_word_addr (matmul_ep_rd_word_addr),
.ep_rd_data (matmul_ep_rd_data),
.ep_rd_ready (matmul_ep_rd_ready),
.ext_rd_req_valid (bridge_cdma_rd_req_valid),
.ext_rd_req_ready (bridge_cdma_rd_req_ready),
.ext_rd_req_src (bridge_cdma_rd_req_src),
.ext_rd_req_bytes (bridge_cdma_rd_req_bytes),
.ext_rd_req_ep_id (bridge_cdma_rd_req_ep_id),
.ext_rd_req_ep_bank (bridge_cdma_rd_req_ep_bank),
.ext_rd_req_ep_word_off(bridge_cdma_rd_req_ep_word_off),
.ext_rd_req_done (bridge_cdma_rd_req_done),
.ext_wr_req_valid (bridge_cdma_wr_req_valid),
.ext_wr_req_ready (bridge_cdma_wr_req_ready),
.ext_wr_req_dst (bridge_cdma_wr_req_dst),
.ext_wr_req_bytes (bridge_cdma_wr_req_bytes),
.ext_wr_req_ep_id (bridge_cdma_wr_req_ep_id),
.ext_wr_req_ep_bank (bridge_cdma_wr_req_ep_bank),
.ext_wr_req_ep_word_off(bridge_cdma_wr_req_ep_word_off),
.ext_wr_req_done (bridge_cdma_wr_req_done),
// 全局中断输出
.dma_finish (cdma_dma_finish)
);
endmodule