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Add CDMA endpoint path for matmul transfers

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FallenSigh
2026-07-01 20:15:55 +08:00
parent 3d39fc2f5e
commit 09fc1aeb44
5 changed files with 439 additions and 56 deletions
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74
rtl/soc_top.v
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@@ -1474,10 +1474,23 @@ mlkem_axi_slave u_mlkem_axi_slave (
.intr (mlkem_intr)
);
//slave 7 - matmul accelerator
matmul_axi_slave u_matmul_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
//slave 7 - matmul accelerator
wire dma_ep_wr_valid;
wire [3:0] dma_ep_wr_id;
wire [3:0] dma_ep_wr_bank;
wire [7:0] dma_ep_wr_word_addr;
wire [31:0] dma_ep_wr_data;
wire dma_ep_wr_ready;
wire dma_ep_rd_valid;
wire [3:0] dma_ep_rd_id;
wire [3:0] dma_ep_rd_bank;
wire [7:0] dma_ep_rd_word_addr;
wire [31:0] dma_ep_rd_data;
wire dma_ep_rd_ready;
matmul_axi_slave u_matmul_axi_slave (
.clk (sys_clk),
.resetn (sys_resetn),
.s_axi_awid (axiOut_7_awid ),
.s_axi_awaddr (axiOut_7_awaddr ),
@@ -1516,11 +1529,25 @@ matmul_axi_slave u_matmul_axi_slave (
.s_axi_rid (axiOut_7_rid ),
.s_axi_rdata (axiOut_7_rdata ),
.s_axi_rresp (axiOut_7_rresp ),
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.intr (matmul_intr)
);
.s_axi_rlast (axiOut_7_rlast ),
.s_axi_rvalid (axiOut_7_rvalid),
.s_axi_rready (axiOut_7_rready),
.ep_wr_valid (dma_ep_wr_valid),
.ep_wr_id (dma_ep_wr_id),
.ep_wr_bank (dma_ep_wr_bank),
.ep_wr_word_addr(dma_ep_wr_word_addr),
.ep_wr_data (dma_ep_wr_data),
.ep_wr_ready (dma_ep_wr_ready),
.ep_rd_valid (dma_ep_rd_valid),
.ep_rd_id (dma_ep_rd_id),
.ep_rd_bank (dma_ep_rd_bank),
.ep_rd_word_addr(dma_ep_rd_word_addr),
.ep_rd_data (dma_ep_rd_data),
.ep_rd_ready (dma_ep_rd_ready),
.intr (matmul_intr)
);
wire [31:0] cdma_s_awaddr;
wire [2:0] cdma_s_awprot;
@@ -1683,12 +1710,25 @@ snix_axil_cdma_mux #(
.mm2mm_rdata (dma_m_rdata),
.mm2mm_rresp (dma_m_rresp),
.mm2mm_rlast (dma_m_rlast),
.mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
.mm2mm_ruser (1'b0),
.mm2mm_rvalid (dma_m_rvalid),
.mm2mm_rready (dma_m_rready),
.ep_wr_valid (dma_ep_wr_valid),
.ep_wr_id (dma_ep_wr_id),
.ep_wr_bank (dma_ep_wr_bank),
.ep_wr_word_addr (dma_ep_wr_word_addr),
.ep_wr_data (dma_ep_wr_data),
.ep_wr_ready (dma_ep_wr_ready),
.ep_rd_valid (dma_ep_rd_valid),
.ep_rd_id (dma_ep_rd_id),
.ep_rd_bank (dma_ep_rd_bank),
.ep_rd_word_addr (dma_ep_rd_word_addr),
.ep_rd_data (dma_ep_rd_data),
.ep_rd_ready (dma_ep_rd_ready),
// 全局中断输出
.dma_finish (dma_finish)
);
// 全局中断输出
.dma_finish (dma_finish)
);
endmodule
endmodule