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fix(fft): update SdfUnit, Twiddle, and axi wrapper

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Ultraworked with [Sisyphus](https://github.com/code-yeongyu/oh-my-openagent)

Co-authored-by: Sisyphus <clio-agent@sisyphuslabs.ai>
This commit is contained in:
FallenSigh
2026-07-05 23:25:51 +08:00
parent e8893a28dd
commit 088a9bd5b8
3 changed files with 40 additions and 22 deletions
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4
rtl/ip/fft/SdfUnit.v
View File

@@ -233,7 +233,9 @@ assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle TW (
Twiddle #(
.WIDTH (WIDTH)
) TW (
.clock (clock ), // i
.addr (tw_addr), // i
.tw_re (tw_re ), // o

11
rtl/ip/fft/Twiddle1024_32B.v
View File

@@ -2,12 +2,13 @@
// Twiddle: 1024-Point Twiddle Table for Radix-2^2 Butterfly
//----------------------------------------------------------------------
module Twiddle #(
parameter TW_FF = 1 // Use Output Register
parameter TW_FF = 1, // Use Output Register
parameter WIDTH = 32
)(
input clock, // Master Clock
input [9:0] addr, // Twiddle Factor Number
output [31:0] tw_re, // Twiddle Factor (Real)
output [31:0] tw_im // Twiddle Factor (Imag)
output [WIDTH-1:0] tw_re, // Twiddle Factor (Real)
output [WIDTH-1:0] tw_im // Twiddle Factor (Imag)
);
wire[31:0] wn_re[0:1023]; // Twiddle Table (Real)
@@ -25,8 +26,8 @@ always @(posedge clock) begin
ff_im <= mx_im;
end
assign tw_re = TW_FF ? ff_re : mx_re;
assign tw_im = TW_FF ? ff_im : mx_im;
assign tw_re = TW_FF ? ff_re[31 -: WIDTH] : mx_re[31 -: WIDTH];
assign tw_im = TW_FF ? ff_im[31 -: WIDTH] : mx_im[31 -: WIDTH];
//----------------------------------------------------------------------
// Twiddle Factor Value

47
rtl/ip/fft/axi_fft_wrapper.v
View File

@@ -7,7 +7,8 @@
(* use_dsp = "no" *)
module fft_controller #(
parameter FFT_LEN = 1024, // FFT处理长度
parameter BRAM_RD_LATENCY = 2 // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2)
parameter BRAM_RD_LATENCY = 2, // 适配 BRAM 的读延迟 (通常 Block RAM 开启输出寄存器为 2)
parameter FFT_DATA_WIDTH = 16
)(
input aclk,
input aresetn,
@@ -226,8 +227,8 @@ module fft_controller #(
reg [10:0] out_cnt;
wire do_en;
wire [31:0] do_re;
wire [31:0] do_im;
wire [FFT_DATA_WIDTH-1:0] do_re;
wire [FFT_DATA_WIDTH-1:0] do_im;
always @(posedge aclk) begin
if (~aresetn) state <= IDLE;
@@ -282,17 +283,22 @@ module fft_controller #(
assign fft_finish = fft_status[1];
// BRAM 接口连线
wire [31:0] in_re_dout;
wire [31:0] in_im_dout;
wire [31:0] out_re_dout;
wire [31:0] out_im_dout;
wire [FFT_DATA_WIDTH-1:0] in_re_dout;
wire [FFT_DATA_WIDTH-1:0] in_im_dout;
wire [FFT_DATA_WIDTH-1:0] out_re_dout;
wire [FFT_DATA_WIDTH-1:0] out_im_dout;
wire [31:0] out_re_sx = {{(32-FFT_DATA_WIDTH){out_re_dout[FFT_DATA_WIDTH-1]}}, out_re_dout};
wire [31:0] out_im_sx = {{(32-FFT_DATA_WIDTH){out_im_dout[FFT_DATA_WIDTH-1]}}, out_im_dout};
my_bram0 u_in0(
my_bram0 #(
.DATA_WIDTH (FFT_DATA_WIDTH),
.ADDR_WIDTH (10)
) u_in0(
.clka (aclk),
.ena (w_active && hit_in_re), // 由 burst写逻辑产生
.wea (1'b1),
.addra (aw_addr_reg[11:2]), // 取当前递增的突发写地址
.dina (s_wdata),
.dina (s_wdata[FFT_DATA_WIDTH-1:0]),
.clkb (aclk),
.enb (state == LOAD),
@@ -300,12 +306,15 @@ module fft_controller #(
.doutb (in_re_dout)
);
my_bram0 u_in1(
my_bram0 #(
.DATA_WIDTH (FFT_DATA_WIDTH),
.ADDR_WIDTH (10)
) u_in1(
.clka (aclk),
.ena (w_active && hit_in_im),
.wea (1'b1),
.addra (aw_addr_reg[11:2]),
.dina (s_wdata),
.dina (s_wdata[FFT_DATA_WIDTH-1:0]),
.clkb (aclk),
.enb (state == LOAD),
@@ -320,7 +329,10 @@ module fft_controller #(
b_rd_addr[5], b_rd_addr[6], b_rd_addr[7], b_rd_addr[8], b_rd_addr[9]
};
my_bram0 u_out0(
my_bram0 #(
.DATA_WIDTH (FFT_DATA_WIDTH),
.ADDR_WIDTH (10)
) u_out0(
.clka (aclk),
.ena (do_en),
.wea (1'b1),
@@ -333,7 +345,10 @@ module fft_controller #(
.doutb (out_re_dout)
);
my_bram0 u_out1(
my_bram0 #(
.DATA_WIDTH (FFT_DATA_WIDTH),
.ADDR_WIDTH (10)
) u_out1(
.clka (aclk),
.ena (do_en),
.wea (1'b1),
@@ -358,7 +373,7 @@ module fft_controller #(
(BRAM_RD_LATENCY == 3) ? di_en_shift[2] : di_en_shift[3];
FFT #(
.WIDTH(32)
.WIDTH(FFT_DATA_WIDTH)
) u_FFT (
.clock (aclk),
.reset (~aresetn),
@@ -373,8 +388,8 @@ module fft_controller #(
// 读取返回数据选择
wire [31:0] rdata_d =
(ar_addr_reg[15:0] == `FFT_CSR_ADDR) ? fft_csr :
hit_out_re ? out_re_dout :
hit_out_im ? out_im_dout :
hit_out_re ? out_re_sx :
hit_out_im ? out_im_sx :
32'h0;
always @(*) begin